1. Field of the Invention
The present invention relates to an improved pipeline computer architecture. More particularly the present invention relates to a pipeline computer architecture in which delays caused by branch instructions are minimized.
2. Art Background
Pipeline computer architectures increase throughput by pipelining instructions through stages. For example, when a first instruction is executing, a second instruction is fetched from memory such that at the completion of execution of the first instruction, the second instruction can be immediately executed. Therefore, the delay that would be incurred by performing the fetch at the time the execution of the first instruction is complete is eliminated. However, a pipeline architecture works only as well as the location of the subsequent instructions can be determined. When the fetch of the next instruction is being performed during execution of the current instruction, the next instruction is typically the next sequential instruction in memory. If a branch instruction occurs, the fetch is aborted and subsequently restarted to fetch the proper instruction as indicated by the branch instruction which had been executed. Therefore, a delay of at least one clock cycle is incurred. The present invention provides for a method and a system for minimizing these delays.